soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• A 40Gb/ s switch IP soft-core with self-dependence intellectual property was realized.
  形成了具有自主知识产权的40Gb/s交换IP软核。
• First some algorithms of gray-scale quantifying are analysised and simulated, and then the detailed designs of complex mold sub-module, quantifying sub-module and SDRAM soft-core controller is presented. 4.
  先对灰度量化算法进行了分析和仿真比较，然后详细介绍了复数求模子模块、量化子模块、SDRAM控制器的设计。
• Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
  详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。
• The paper introduces the structural features of the network processor Nios II and customized instructions and design methods for forwarding software of the network processor based on the Nios II soft-core processor and design methods for the DSP processor used for the processing of the video and image data.
  文中介绍了网络处理器NIOSii的结构特点和自定义指令以及基于NIOSii软核处理器的网络处理器转发软件的设计方法和基于视频图像处理的DSP处理器的设计方法。
• The Nios ⅱ soft-core processor improve the integration of the system and is helpful to the miniaturization of instrument.
  NiosⅡ软核处理器提高了系统的集成度，有利于系统的小型化，降低了成本。
• Research and Design of Soft-core IP for AVS Inter Decoder
  AVS帧间解码IP软核的研究与设计
• For the digital part, this design is mean to construct the SOPC system in the FPGA, embedded Nios II soft-core processor to control the operation of the entire system.
  对于数字部分，在FPGA内构建SOPC系统，嵌入NIOSii软核处理器对整个系统进行控制。
• This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
  提出了一种基于FPGA（现场可编程门阵列）和软核CPU的嵌入式系统设计的新方法。
• With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
  通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
• Design of an Ethernet Interface Based on the Nios Soft-core Processor
  基于Nios软核处理器的以太网接口设计